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SN74HC10N - TRIPLE 3-INPUT POSITIVE-NAND GATES

Download the SN74HC10N datasheet PDF. This datasheet also covers the SN74HC10 variant, as both devices belong to the same triple 3-input positive-nand gates family and are provided as variant models within a single manufacturer datasheet.

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Note: The manufacturer provides a single datasheet file (SN74HC10-etcTI.pdf) that lists specifications for multiple related part numbers.

General Description

This device contains three independent 3-input NAND gates.

Each gate performs the Boolean function Y = A ● B ● C in positive logic.

Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN74HC10D SOIC (14) 8.70 mm × 3.90 mm SN74HC10N PDIP (14) 19.30 mm × 6.40 mm SN74HC10NS SO (14) 10.20 mm × 5.30 mm SN74HC10PW TSSOP (14) 5.00 mm × 4.40 mm SN54HC10J CDIP (14) 21.30 mm × 7.60 mm SN54HC10FK LCCC (20) 8.90 mm × 8.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet.

Overview

www.ti.com SCLS083E – DECEMBERSS1NN9877244–HHRCCEV11I00S,,ESSDNNAP55R44IHHL CC20112001 SCLS083E – DECEMBER 1982 – REVISED APRIL 2021 SNx4HC10 Triple 3-Input NAND Gates.

Key Features

  • Buffered inputs.
  • Wide operating voltage range: 2 V to 6 V.
  • Wide operating temperature range:.
  • 40°C to +85°C.
  • Supports fanout up to 10 LSTTL loads.
  • Significant power reduction compared to LSTTL logic ICs 2.

More Datasheets from Texas Instruments

Part Number Description
SN74HC10 Triple 3-Input NAND Gates
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SN74HC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
SN74HC109N DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
SN74HC10D Triple 3-Input NAND Gates
SN74HC11 Triple 3-Input AND Gates
SN74HC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
SN74HC112N DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
SN74HC125 Quadruple Buffers