SN74HC138-Q1 Datasheet | Texas Instruments

SN74HC138-Q1 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 p F, R = 0) D Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems D 2-V to 6-V VCC Operation D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 15 ns D ±4-m A Output Drive at 5 V D Low Input Current of 1 µA Max D Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception SCLS533A - AUGUST 2003 - REVISED SEPTEMBER 2008 D OR PW PACKAGE (TOP VIEW) A B C G2A G2B G1 Y7 GND 1 2 3 4 5 6 7 8 16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 description/ordering information The SN74HC138 is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. ORDERING INFORMATION{ PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC - D - 40°C to 125°C TSSOP - PW Tape and reel Tape and reel SN74HC138QDRQ1 SN74HC138QPWRQ1 HC138Q1 HC138Q1 † For the most current package and ordering information, see the Package Option Addendum at the...