SN74LV245AT Datasheet | Texas Instruments

.ti. SCLS605D - DECEMBER 2004 - REVISED JULY 2013 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS Check for Samples: SN74LV245AT Features - Inputs Are TTL-Voltage patible - 4.5-V to 5.5-V VCC Operation - Typical tpd of 3.5 ns at 5 V - Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 5 V, TA = 25°C - Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 5 V, TA = 25°C - Supports Mixed-Mode Voltage Operation on All Ports - Ioff Supports Partial-Power-Down Mode Operation - Latch-Up Performance Exceeds 250 m A Per JESD 17 - ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 1000-V Charged-Device Model (C101) DESCRIPTION This octal bus transceiver is designed for asynchronous two-way munication between data buses. The control-function implementation minimizes external timing requirements. The SN74LV245AT allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 OE 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 B8 RGY PACKAGE (TOP VIEW) A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8...