SN74LV74
SN74LV74 is DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS manufactured by Texas Instruments.
description
These dual positive-edge-triggered D-type flipflops are designed for 2.7-V to 5.5-V VCC operation.
SN54LV74 . . . J OR W PACKAGE SN74LV74 . . . D, DP, OR PW PACKAGE
(TOP VIEW)
1CLR 1 1D 2
1CLK 3 1PRE 4
1Q 5 1Q 6 GND 7
14 VCC 13 2CLR 12 2D 11 2CLK 10 2PRE 9 2Q 8 2Q
SN54LV74 . . . FK PACKAGE (TOP VIEW)
1D 1CLR NC VCC 2CLR
1CLK NC
1PRE NC 1Q
3 2 1 20 19
9 10 11 12 13
2D NC 2CLK NC 2PRE
1Q GND
NC 2Q 2Q
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are
- No internal connection inactive (high), data at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
The SN74LV74 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV74 is characterized for operation over the full military temperature range of
- 55°C to 125°C. The SN74LV74 is characterized for operation from
- 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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