SN74LV8154-EP Datasheet | Texas Instruments

D Controlled Baseline - One Assembly Site - One Test Site - One Fabrication Site D Extended Temperature Performance of - 55°C to 125°C D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Product-Change Notification D Qualification Pedigree† D Can Be Used as Two 16 Bit Counters or a Single 32 Bit Counter D 2-V to 5.5-V VCC Operation D Max tpd of 25 ns at 5 V (RCLK to Y) D Typical VOLP (Output Ground Bounce) <0.7 V at VCC = 5 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) >4.4 V at VCC = 5 V, TA = 25°C D Ioff Supports Partial-Power-Down Mode Operation D Latch-Up Performance Exceeds 250 m A Per JESD 17 SN74LV8154ĆEP DUAL 16 BIT BINARY COUNTER WITH 3ĆSTATE OUTPUT REGISTERS SCLS704A - JULY 2006 - REVISED SEPTEMBER 2007 D ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) † ponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold pound life. Such qualification testing should not be viewed as justifying use of this ponent beyond specified performance and environmental limits. PW PACKAGE (TOP...