SN74LVC00A-EP Datasheet | Texas Instruments

FEATURES - Controlled Baseline - One Assembly/Test Site, One Fabrication Site - Extended Temperature Performance of - 40°C to 125°C and - 55°C to 125°C - Enhanced Diminishing Manufacturing Sources (DMS) Support - Enhanced Product-Change Notification - Qualification Pedigree (1) - ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 p F, R = 0) - Operates From 2 V to 3.6 V - Inputs Accept Voltages to 5.5 V - Max tpd of 4.3 ns at 3.3 V (1) ponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold pound life. Such qualification testing should not be viewed as justifying use of this ponent beyond specified performance and environmental limits. SN74LVC00A-EP QUADRUPLE 2-INPUT POSITIVE-NAND GATE SCAS729B - NOVEMBER 2003 - REVISED MARCH 2007 - Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C D OR PW PACKAGE (TOP VIEW) 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y DESCRIPTION /ORDERING INFORMATION The SN74LVC00A quadruple 2-input positive-NAND gate is designed for 2.7-V to 3.6-V VCC operation. The device performs the Boolean function Y = A ⋅ B or Y = A + B in positive logic. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. ORDERING INFORMATION(1) - 40 °C to 125 °C - 55 °C to 125 °C SOIC - D TSSOP - PW TSSOP - PW PACKAGE (2) Reel of 2500 Reel of 2000 Reel of 2000 ORDERABLE PART NUMBER SN74LVC00AQDREP SN74LVC00AQPWREP SN74LVC00AMPWREP TOP-SIDE MARKING LVC00AE LVC00AE LVC00AM (1) For the most current package and ordering information,...