SN74LVC74A-Q1 Datasheet | Texas Instruments

FEATURES - Qualified for Automotive Applications - ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 p F, R = 0) - Operates From 2 V to 3.6 V - Inputs Accept Voltages to 5.5 V - Max tpd of 5.2 ns at 3.3 V - Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C D OR PW PACKAGE (TOP VIEW) 1CLR 1 1D 2 1CLK 3 1PRE 4 1Q 5 1Q 6 GND 7 14 VCC 13 2CLR 12 2D 11 2CLK 10 2PRE 9 2Q 8 2Q DESCRIPTION /ORDERING INFORMATION The SN74LVC74A-Q1 dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. - 40°C to 125°C SOIC - D TSSOP - PW ORDERING INFORMATION(1) PACKAGE (2) ORDERABLE PART NUMBER Reel of 2500 SN74LVC74AQDRQ1 Reel of 2000 SN74LVC74AQPWRQ1 TOP-SIDE MARKING LVC74AQ LVC74AQ (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at .ti.. (2) Package drawings, thermal data, and symbolization are available at .ti./packaging. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this...