SN74LVCZ161284A Datasheet | Texas Instruments

FEATURES - Power-On Reset (POR) Prevents Printer Errors When Printer Is Turned On, But No Valid Signal Is at Pins A9- A13 - Operates From 3 V to 3.6 V - 1.4-kΩ Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors - Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications - Flow-Through Architecture Optimizes PCB Layout - Ioff and Power-Up 3-State Support Hot Insertion - Latch-Up Performance Exceeds 100 m A Per JESD 78, Class II - ESD Protection Exceeds JESD 22 - 4000-V Human-Body Model (A114-A) - 350-V Machine Model (A115-A) - 1500-V Charged-Device Model (C101) DESCRIPTION /ORDERING INFORMATION The SN74LVCZ161284A is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way munication between data buses. The control-function implementation minimizes external timing requirements. DGG PACKAGE (TOP VIEW) HD 1 A9 2 A10 3 A11 4 A12 5 A13 6 VCC 7 A1 8 A2 9 GND 10 A3 11 A4 12 A5 13 A6 14 GND 15 A7 16 A8 17 VCC 18 PERI LOGIC IN 19 A14 20 A15 21 A16 22 A17 23 HOST LOGIC OUT 24 48 DIR 47 Y9 46 Y10 45 Y11 44 Y12 43 Y13 42 VCC CABLE 41 B1 40 B2 39 GND 38 B3 37 B4 36 B5 35 B6 34 GND 33 B7 32 B8 31 VCC CABLE 30 PERI LOGIC OUT 29 C14 28 C15 27 C16 26 C17 25 HOST LOGIC IN This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control (DIR) input is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side and four receivers. The SN74LVCZ161284A has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line. The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface...