Overview: SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512
3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 D Members of the Texas Instruments
SCOPE ™ Family of Testability Products
D Members of the Texas Instruments
Widebus ™ Family
D State-of-the-Art 3.3-V ABT Design Supports
Mixed-Mode Signal Operation (5-V Input
and Output Voltages With 3.3-V VCC)
D Support Unregulated Battery Operation
Down to 2.7 V
D UBT ™ (Universal Bus Transceiver)
bines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D B-Port Outputs of ’LVTH182512 Devices
Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required
D patible With the IEEE Std 1149.1-1990
(JTAG) Test Access Port and
Boundary-Scan Architecture
D SCOPE ™ Instruction Set
– IEEE Std 1149.1-1990 Required
Instructions and Optional CLAMP and
HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
D Package Options Include 64-Pin Plastic
Thin Shrink Small Outline (DGG) and 64-Pin
Ceramic Dual Flat (HKC) Packages Using
0.5-mm Center-to-Center Spacings SN54LVTH18512, SN54LVTH182512 . . . HKC PACKAGE SN74LVTH18512, SN74LVTH182512 . . .
