SN74LVTH273-EP Datasheet | Texas Instruments

description /ordering information This octal D-type flip-flop is designed specifically for low-voltage (3.3 V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVTH273 is a positive-edge-triggered flip-flop with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not remended. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING - 40°C to 85°C TSSOP - PW Tape and reel SN74LVTH273IPWREP LH273EP - 55°C to 125°C SOP - NS Tape and reel SN74LVTH273MNSREP LVTH273EP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at .ti./sc/package. Please be aware that an important notice concerning availability,...