SN74SSQEA32882 Overview
All inputs are 1.5 V and 1.35 V CMOS patible. All outputs are CMOS drivers optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications. The clock outputs Yn and Yn and control net outputs DxCKEn, DxCSn and DxODTn can be driven with a different strength and skew to optimize signal integrity, pensate for different loading and equalize signal travel speed.
SN74SSQEA32882 Key Features
- JEDEC SSTE32882 pliant
- 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs
- CKE Powerdown Mode for Optimized System Power Consumption
- 1.5V/1.35V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distributing to Four D
- 1.5V/1.35V CMOS Inputs
- Checks Parity on mand and Address
- Configurable Driver Strength
- Uses Internal Feedback Loop
SN74SSQEA32882 Applications
- DDR3 Registered DIMMs up to DDR3-1600
- DDR3L Registered DIMMs up to DDR3L-1333