SN74SSTEB32866 Description
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.425-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.
SN74SSTEB32866 Key Features
- 2 Member of the Texas Instruments Widebus+™ Family
- Pinout Optimizes DDR2 DIMM PCB Layout
- Configurable as 25-Bit 1:1 or 14-Bit 1:2
- Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption
- Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line
- Supports 1.5V and 1.8V Supply Voltage Range
- Differential Clock (CLK and CLK) Inputs
- Supports LVCMOS Switching Levels on the
- Checks Parity on DIMM-Independent Data Inputs
- Able to Cascade With a Second SN74SSTEB32866