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SN74SSTUB32866 - 25-BIT CONFIGURABLE REGISTERED BUFFER

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Overview

SN74SSTUB32866 www.ti.com SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY.

Key Features

  • 1.
  • 2 Member of the Texas Instruments Widebus+™ Family.
  • Pinout Optimizes DDR2 DIMM PCB Layout.
  • Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer.
  • Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption.
  • Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line.
  • Supports SSTL_18 Data Inputs.
  • Differential Clock (CLK and CLK) Inputs.
  • Supports LVCMOS Switc.

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