SN74SSTV32867-EP Description
/ORDERING INFORMATION This 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled LVCMOS circuits optimized for unterminated DIMM loads.
SN74SSTV32867-EP Key Features
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of -40°C to 85°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product Change Notification
- Qualification Pedigree (1)
- Member of the Texas Instruments Widebus+™ Family
- Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated DIMM Load
- Supports SSTL_2 Data Inputs
- Differential Clock (CLK and CLK) Inputs