SN74SSTVF32852 Overview
/ordering information This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled circuits, optimized for unterminated DIMM loads, and meet SSTL_2 Class I specifications.