SN75C091A Datasheet | Texas Instruments

Description The SN75C091A provides the capability to interface a microprocessor subsystem to the ANSI Small puter Systems Interface (SCSI). This single-ended SCSI implementation acts as one of up to eight nodes municating over a maximum six-meter bus as detailed in the SCSI specification (ANSI X3.131-1986). Its microprocessor and DMA interfaces allow the SN75C091A SCSI Bus Controller (SBC) to be used in a variety of host or peripheral applications. This document is not intended to serve as a tutorial on the Small puter Systems Interface bus; users should refer to ANSI X3.131-1986 for detailed information regarding the SCSI bus. 1.2 Features - - - - - - - - - - SCSI Bus Interface plies with ANSI X3.131-1986 SCSI standard Performs INITIATOR and TARGET functions Supports arbitration, selection, and reselection Performs asynchronous data transfers of up to 5 Megabytes/second (MBps) Performs synchronous data transfers of up to 5 Megabytes/second (MBps) with programmable offset up to 15 Has on-chip 48-m A transceivers Provides optional parity generation, checking, and pass-through Reduces overhead associated with initiator multi-threading by automatically handling savedata-pointer messages, disconnects, and reconnects Performs automatic message and mand-length decoding Has two 32-byte FIFOs for mand and message preloading - - - - - - - - - Microprocessor Interface Provides chip control via directly-addressable registers Has optional address latch line for multiplexed address/data buses Allows DMA- or programmed-I/O data transfers Is interrupt-driven to minimize host polling Can execute multi-phase mands to minimize interrupts Has 24-bit transfer counter Provides byte-stacking control to acmodate 8-, 16-, and 32-bit systems Offers optional parity generation and checking Is equipped with separate ports for DMA and microprocessor interfacing - - - General Requires a single 5 V ± 5% power supply Low-power CMOS technology 68-pin PLCC package 1- 1 1-...