SN75C091A Overview
Key Specifications
Package: PLCC
Key Features
- SCSI Bus Interface Complies with ANSI X3.131-1986 SCSI standard Performs INITIATOR and TARGET functions Supports arbitration, selection, and reselection Performs asynchronous data transfers of up to 5 Megabytes/second (MBps) Performs synchronous data transfers of up to 5 Megabytes/second (MBps) with programmable offset up to 15 Has on-chip 48-mA transceivers Provides optional parity generation, checking, and pass-through Reduces overhead associated with initiator multi-threading by automatically handling savedata-pointer messages, disconnects, and reconnects Performs automatic message and command-length decoding Has two 32-byte FIFOs for command and message preloading
- Microprocessor Interface Provides chip control via directly-addressable registers Has optional address latch line for multiplexed address/data buses Allows DMA- or programmed-I/O data transfers Is interrupt-driven to minimize host polling Can execute multi-phase commands to minimize interrupts Has 24-bit transfer counter Provides byte-stacking control to accommodate 8-, 16-, and 32-bit systems Offers optional parity generation and checking Is equipped with separate ports for DMA and microprocessor inter
