SN75LVDT388 Datasheet | Texas Instruments

SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS D Eight Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard D Integrated 110-Ω Line Termination Resistors on LVDT Products D Designed for Signaling Rates† Up To 630 Mbps D SN65 Version’s Bus-Terminal ESD Exceeds 15 kV D Operates From a Single 3.3-V Supply D Propagation Delay Time of 2.6 ns (Typ) D Output Skew 100 ps (Typ) Part-To-Part Skew Is Less Than 1 ns D LVTTL Levels Are 5-V Tolerant D Open-Circuit Fail Safe D Flow-Through Pin Out D Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch description The ‘LVDS388 and ‘LVDT388 (T designates integrated...