SNJ54HCT74J Overview
The ’HCT74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse.
SNJ54HCT74J Key Features
- Operating voltage range of 4.5 V to 5.5 V
- Outputs can drive up to 10 LSTTL loads
- Low power consumption, 40-μA max ICC
- Typical tpd = 17 ns
- ±4-mA output drive at 5 V
- Low input current of 1 μA max
- Inputs are TTL-voltage patible