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TCI6638K2K - Multicore DSP+ARM KeyStone II SoC

Datasheet Summary

Description

The TCI6638K2K Communications Infrastructure KeyStone SoC is a member of the C66x family based on TI's new KeyStone II Multicore SoC Architecture designed specifically for high-performance wireless infrastructure applications.

Features

  • 1.
  • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With.
  • 1.0 GHz or 1.2 GHz C66x Fixed- and FloatingPoint DSP Core.
  • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz.
  • 19.2 GFlops/Core for Floating Point @ 1.2 GHz.
  • Memory.
  • 32-KB L1P Per CorePac.
  • 32-KB L1D Per CorePac.
  • 1024-KB Local L2 Per CorePac.
  • ARM CorePac.
  • Four ARM® Cortex®-A15 MPCore™ Processors at up to 1.4 GHz.
  • 4MB of L2 Cache Memory Share.

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Datasheet Details

Part number TCI6638K2K
Manufacturer Texas Instruments
File Size 2.23 MB
Description Multicore DSP+ARM KeyStone II SoC
Datasheet download datasheet TCI6638K2K Datasheet
Additional preview pages of the TCI6638K2K datasheet.

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Product Folder Order Now Technical Documents Tools & Software Support & Community TCI6638K2K SPRS836G – NOVEMBER 2012 – REVISED OCTOBER 2017 TCI6638K2K Multicore DSP+ARM® KeyStone™ II System-on-Chip (SoC) 1 Device Overview 1.1 Features 1 • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With – 1.0 GHz or 1.2 GHz C66x Fixed- and FloatingPoint DSP Core – 38.4 GMacs/Core for Fixed Point @ 1.2 GHz – 19.2 GFlops/Core for Floating Point @ 1.2 GHz – Memory – 32-KB L1P Per CorePac – 32-KB L1D Per CorePac – 1024-KB Local L2 Per CorePac • ARM CorePac – Four ARM® Cortex®-A15 MPCore™ Processors at up to 1.4 GHz – 4MB of L2 Cache Memory Shared by Four ARM Cores – Full Implementation of ARMv7-A Architecture Instruction Set – 32-KB L1 Instruction and Data Caches per Core – AMBA 4.
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