TDA4VM Overview
TDA4VM Processors TDA4VM-Q1, TDA4VM SPRSP36K SEPTEMBER 2021 REVISED APRIL 2024.
TDA4VM Key Features
- C7x floating point, vector DSP, up to 1.0GHz, 80 GFLOPS, 256 GOPS
- Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0GHz
- Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators
- Depth and Motion Processing Accelerators (DMPAC)
- Dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2.0GHz
- 1MB shared L2 cache per dual-core Cortex®A72 cluster
- 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 core
- Six Arm® Cortex®-R5F MCUs at up to 1.0GHz
- 16K I-Cache, 16K D-Cache, 64K L2 TCM
- Two Arm® Cortex®-R5F MCUs in isolated MCU
TDA4VM Applications
- Documentation will be available to aid ISO
- Systematic capability up to ASIL-D/SC-3 targeted
- Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
- Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
