TICPAL22V10Z-30I Datasheet | Texas Instruments

TICPAL22V10Z-25C, TICPAL22V10Z-30I EPIC™ CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS007D - D3323, SEPTEMBER 1989 - REVISED DECEMBER 2010 - 24-Pin Advanced CMOS PLD - Virtually Zero Standby Power - Propagation Delay Time: I, I/O to I/O in the Turbo Mode -25C . . . 25 ns Max -30I . . . 30 ns Max I, I/O to I/O in the Zero-Power Mode -25C . . . 35 ns Max -30I . . . 40 ns Max CLK to Q -25C . . . 15 ns Max -30I . . . 20 ns Max - Variable Product Term Distribution Allows More plex Functions to Be Implemented - Each Output Is User-Programmable for Registered or binatorial Operation, Polarity, and Output Enable Control - Extra Terms Provide Logical Synchronous Set and Asynchronous Reset Capability - Preload Capability on All Registered Outputs Allow for Improved Device Testing - UV Light Erasable Cell Technology Allows for: Reconfigurable Logic Reprogrammable Cells Full Factory Testing for High Programming Yield - Programmable Design Security Bit Prevents Copying of Logic Stored in Device - Package Options Include Plastic Dual-In-Line and Clip Carrier [for One-Time-Programmable (OTP) Devices] and Ceramic Dual-In-Line Windowed Package . AVAILABLE OPTIONS JTL AND NT PACKAGE (TOP VIEW) CLK/I 1 I2 I3 I4 I5 I6 I7 I8 I9 I 10 I 11 GND 12 24 VCC 23 I/O/Q 22 I/O/Q 21 I/O/Q 20 I/O/Q 19 I/O/Q 18 I/O/Q 17 I/O/Q 16 I/O/Q 15 I/O/Q 14 I/O/Q 13...