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TL16C754BPN - DUAL UART

Download the TL16C754BPN datasheet PDF. This datasheet also covers the TL16C754B variant, as both devices belong to the same dual uart family and are provided as variant models within a single manufacturer datasheet.

General Description

The TL16C754B is a quad universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 3 Mbps.

Key Features

  • It has a transmission control register (TCR) that stores received FIFO threshold level to start/stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TL16C754B-etcTI.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TL16C754B QUAD UART WITH 64ĆBYTE FIFO D ST16C654 Pin Compatible With Additional Enhancements D Supports Up To 24-MHz Crystal Input Clock ( 1.5 Mbps) D Supports Up To 48-MHz Oscillator Input Clock ( 3 Mbps) for 5-V Operation D Supports Up To 32-MHz Oscillator Input Clock ( 2 Mbps) for 3.3-V Operation D 64-Byte Transmit FIFO D 64-Byte Receive FIFO With Error Flags D Programmable and Selectable Transmit and Receive FIFO Trigger Levels for DMA and Interrupt Generation D Programmable Receive FIFO Trigger Levels for Software/Hardware Flow Control D Software/Hardware Flow Control − Programmable Xon/Xoff Characters − Programmable Auto-RTS and Auto-CTS D Optional Data Flow Resume by Xon Any Character D DMA Signalling Capability for Both Received and Transmitted Data D Supports 3.