TLK1002A Description
TLK1002A is a single-chip dual signal conditioning transceiver. This chip supports data rates from 1.0 Gbps up to 1.3 Gbps. An on-chip clock generation phase-locked loop (PLL) generates the required half-rate clock from an externally applied reference clock.
TLK1002A Key Features
- Fully Integrated Signal Conditioning Transceiver
- 1.0-1.3 Gbps Operation
- Low Power CMOS Design (<300 mW)
- High Differential Output Voltage Swing
- 400 mVp-p Differential Input Sensitivity
- High Input Jitter Tolerance 0.606 UI
- Single 1.8 V Power Supply
- 2.5 V Tolerant Control Inputs
- Differential VML Transmit Outputs With No
- JUNE 2005
TLK1002A Applications
- Resynchronization in Both Directions for 1.25 Gbps Links
- Repeater for 1.0625 Gbps Applications