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TLK1002A - DUAL SIGNAL CONDITIONING TRANSCEIVER

General Description

TLK1002A is a single-chip dual signal conditioning transceiver.

This chip supports data rates from 1.0 Gbps up to 1.3 Gbps.

An on-chip clock generation phase-locked loop (PLL) generates the required half-rate clock from an externally applied reference clock.

Key Features

  • Fully Integrated Signal Conditioning Transceiver.
  • 1.0.
  • 1.3 Gbps Operation.
  • Low Power CMOS Design (.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.ti.com FEATURES • Fully Integrated Signal Conditioning Transceiver • 1.0–1.3 Gbps Operation • Low Power CMOS Design (<300 mW) • High Differential Output Voltage Swing (1600 mVp-p typical) • 400 mVp-p Differential Input Sensitivity • High Input Jitter Tolerance 0.606 UI • Single 1.8 V Power Supply • 2.5 V Tolerant Control Inputs • Differential VML Transmit Outputs With No External Components Necessary TLK1002A DUAL SIGNAL CONDITIONING TRANSCEIVER SLLS661 – JUNE 2005 • No External Filter Components Required for PLLs • Supports Loop-Back Modes • Temperature Rating 0°C to 70°C • Small Footprint 4 mm × 4 mm 24-Lead QFN Package APPLICATIONS • Resynchronization in Both Directions for 1.25 Gbps Links • Repeater for 1.