TLV320AIC13 Texas Instruments Datasheet

TLV320AIC13 Key Features

• Mono 16-Bit Oversampling Sigma-Delta A/D Converter
• Mono 16-Bit Oversampling Sigma-Delta D/A Converter
• Support Maximum Master Clock of 100 MHz to Allow the DSP Output Clock to be Used as a Master Clock
• Selectable FIR/IIR Filter With Bypassing Option
• Max 26 Ksps With On-Chip IIR/FIR Filter
• Max 104 Ksps With IIR/FIR Bypassed
• On-Chip FIR Produced 84-dB SNR for ADC and 92-dB SNR for DAC
• Smart Time Division Multiplexed (SMARTDM™) Serial Port
• Glueless 4-Wire Interface to DSP
• Automatic Cascade Detection (ACD) Self-Generates Master/Slave Device Addresses