Datasheet Summary
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TLV320AIC20, TLV320AIC21 TLV320AIC24, TLV320AIC25 TLV320AIC20K, TLV320AIC24K
SLAS363D
- MARCH 2002
- REVISED APRIL 2005
Low-Power, Highly-Integrated, Programmable 16-Bit, 26-KSPS, Dual-Channel CODEC
Features
- Stereo 16-Bit Oversampling Sigma-Delta A/D Converter
- Stereo 16-Bit Oversampling Sigma-Delta D/A Converter
- Support Maximum Master Clock of 100 MHz to Allow DSPs Output Clock to be Used as a Master Clock
- Selectable FIR/IIR Filter With Bypassing Option
- Programmable Sampling Rate up to:
- Max 26 Ksps With On-Chip IIR/FIR Filter
- Max 104 Ksps With IIR/FIR Bypassed
- On-Chip FIR Produced 84-dB SNR for ADC and 92-dB SNR for DAC over 13-Khz BW
- Smart Time Division...