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TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS
D Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and One Program Memory Bus
D 40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
D 17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
D Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi Operator
D Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
D Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
D Data Bus With a Bus Holder Feature D Address Bus With a Bus Holder Fe
TMS320C541 Datasheet
