TMS320C6415T Datasheet | Texas Instruments

Features - Byte-Addressable (8-/16-/32-/64-Bit Data) - 8-Bit Overflow Protection - Bit-Field Extract, Set, Clear - Normalization, Saturation, Bit-Counting - Veloci TI.2 Increased Orthogonality D Host-Port Interface (HPI) - User-Configurable Bus Width (32-/16-Bit) D 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415T/C6416T] - Three PCI Bus Address Registers: Prefetchable Memory Non-Prefetchable Memory I/O - Four-Wire Serial EEPROM Interface - PCI Interrupt Request Under DSP Program Control - DSP Interrupt Via PCI I/O Cycle D Three Multichannel Buffered Serial Ports - Direct Interface to T1/E1, MVIP, SCSA Framers - Up to 256 Channels Each - ST-Bus-Switching-, AC97-patible - Serial Peripheral Interface (SPI) patible (Motorola) D Three 32-Bit General-Purpose Timers D UTOPIA [C6415T/C6416T] D VCP [C6416T Only] - Supports Over 833 7.95-Kbps AMR - Programmable Code Parameters D TCP [C6416T Only] - Supports up to 10 2-Mbps or 60 384-Kbps 3GPP (6 Iterations) - UTOPIA Level 2 Slave ATM Controller - 8-Bit Transmit and Receive Operations up to 50 MHz per Direction - User-Defined Cell Format up to 64 Bytes D Sixteen General-Purpose I/O (GPIO) Pins D Flexible PLL Clock Generator - Programmable Turbo Code and Decoding Parameters D L1/L2 Memory Architecture - 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped) - 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative) - 8M-Bit (1024K-Byte) L2 Unified Mapped D IEEE-1149.1 (JTAG†) Boundary-Scan-patible D 532-Pin Ball Grid Array (BGA) Package (GLZ/ZLZ/CLZ Suffixes), 0.8-mm...