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TMS320F28026F - Microcontroller

Download the TMS320F28026F datasheet PDF. This datasheet also covers the TMS320F28027 variant, as both devices belong to the same microcontroller family and are provided as variant models within a single manufacturer datasheet.

General Description

C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closedloop performance in real-time control applications such as industrial motor drives; solar inverters and digital power; electrical vehicles and transportation; motor control; and sensing and signal pr

Key Features

  • 1.
  • High-efficiency 32-bit CPU (TMS320C28x).
  • 60 MHz (16.67-ns cycle time).
  • 50 MHz (20-ns cycle time).
  • 40 MHz (25-ns cycle time).
  • 16 × 16 and 32 × 32 MAC operations.
  • 16 × 16 dual MAC.
  • Harvard bus architecture.
  • Atomic operations.
  • Fast interrupt response and processing.
  • Unified memory programming model.
  • Code-efficient (in C/C++ and Assembly).
  • Endianness: Little endian.
  • Low cost for bo.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TMS320F28027-etcTI.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Texas Instruments

Part Number Description
TMS320F28026F Microcontrollers
TMS320F28026F-Q1 Microcontrollers
TMS320F28026 Microcontrollers
TMS320F28026-Q1 Microcontrollers
TMS320F280260 Microcontrollers

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Product Folder Order Now Technical Documents Tools & Software Support & Community TMS320F28027, TMS320F28027F, TMS320F28026, TMS320F28026F, TMS320F28023 TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200 SPRS523N – NOVEMBER 2008 – REVISED JUNE 2020 TMS320F2802x Microcontrollers 1 Device Overview 1.1 Features 1 • High-efficiency 32-bit CPU (TMS320C28x) – 60 MHz (16.67-ns cycle time) – 50 MHz (20-ns cycle time) – 40 MHz (25-ns cycle time) – 16 × 16 and 32 × 32 MAC operations – 16 × 16 dual MAC – Harvard bus architecture – Atomic operations – Fast interrupt response and processing – Unified memory programming model – Code-efficient (in C/C++ and Assembly) • Endianness: Little endian • Low cost for both device and system: – Single 3.