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• Two 7.5-A Independent Output Channels,
Continuous Current Per Channel
• Low rDS(on) . . . 0.09 Ω Typical • Output Voltage . . . 60 V • Pulsed Current . . . 15 A Per Channel • Avalanche Energy . . . 120 mJ
description
The TPIC5201 is a power monolithic DMOS array that consists of dual independent N-channel enhancement-mode DMOS transistors.
schematic
DRAIN1 3
GATE2
DRAIN2 56
GATE1
1
TPIC5201 DUAL POWER DMOS ARRAY
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SLIS020 − SEPTEMBER 1992
KV PACKAGE (TOP VIEW)
7 SOURCE2
6 DRAIN2
5 GATE2
4 GND
3 DRAIN1
2 1
SOURCE1 GATE1
To ensure correct device operation, the source and the drain of the same transistor cannot simultaneously be taken below GND.
The tab is electrically connected to GND.