TPS53625 Datasheet | Texas Instruments

SLUSEW7 - JUNE 2022 TPS53625 2-Phase, D-CAP+™ Step-Down Controller for VR12.0 VCPU 1 Features - VR12.0 serial VID (SVID) pliant - 1- or 2-phase operation - Supports both zero-load and non-zero-load line applications - 8-Bit DAC output range: 0.25 V to 1.52 V - Optimized efficiency at light and heavy loads - 8 independent levels of overshoot reduction (OSR) and undershoot reduction (USR) - Driverless configuration for efficient high-frequency switching - Supports discrete, Power Block, Power Stage or Dr MOS MOSFET implementations - Accurate, adjustable voltage positioning - 300-k Hz to 1-MHz frequency selections - Patented Auto Balance Phase Balancing - Selectable 8-level current limit - 4.5-V to 28-V conversion voltage range - Small, 4 mm × 4 mm, 32-Pin, VQFN Power PAD™ integrated circuit package 2 Applications - Core Memory 3 Description The TPS53625 device is a driverless, fully SVID pliant, VR12.0 step-down controller. Advanced control Features such as D-CAP+ architecture with overlapping pulse support undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, lowest output capacitance and high efficiency. The TPS53625 device also supports single-phase operation in CCM or DCM for lightload efficiency. The TPS53625 device integrates the full plement of VR12.0 I/O Features including VR_READY (PGOOD), ALERT and VR_HOT. The SVID interface address allows programming from 0 to 7. Adjustable control of VOUT slew rate and voltage positioning round out the VR12.0 Features . Paired with the TPS51604 FET gate driver, the solution delivers exceptionally high speed and low switching loss. The TPS53625 device works with selected TI power stage products for optimum efficiency as well as Dr MOS products. The TPS53625 device operates with a default boot voltage of 1 V. Applications can override the default boot voltage by including an external resistor divider in the design. The TPS53625 device package is a space saving, thermally...