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74AHC02BQ - Quad 2-input NOR gate

Download the 74AHC02BQ datasheet PDF. This datasheet also covers the 74AHC02 variant, as both devices belong to the same quad 2-input nor gate family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

It is specified in compliance with JEDEC standard No.

7-A.

Key Features

  • Balanced propagation delays.
  • All inputs have a Schmitt-trigger action.
  • Inputs accept voltages higher than VCC.
  • Input levels:.
  • For 74AHC02: CMOS level.
  • For 74AHCT02: TTL level.
  • ESD protection:.
  • HBM EIA/JESD22-A114E exceeds 2000 V.
  • MM EIA/JESD22-A115-A exceeds 200 V.
  • CDM EIA/JESD22-C101C exceeds 1000 V.
  • Multiple package options.
  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC02-nexperia.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Nexperia

Part Number Description
74AHC02 Quad 2-input NOR gate
74AHC02-Q100 Quad 2-input NOR gate
74AHC02D Quad 2-input NOR gate
74AHC00 Quad 2-input NAND gate
74AHC00-Q100 Quad 2-input NAND gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74AHC02; 74AHCT02 Quad 2-input NOR gate Rev. 5 — 11 May 2020 Product data sheet 1. General description The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function. 2. Features and benefits • Balanced propagation delays • All inputs have a Schmitt-trigger action • Inputs accept voltages higher than VCC • Input levels: • For 74AHC02: CMOS level • For 74AHCT02: TTL level • ESD protection: • HBM EIA/JESD22-A114E exceeds 2000 V • MM EIA/JESD22-A115-A exceeds 200 V • CDM EIA/JESD22-C101C exceeds 1000 V • Multiple package options • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3.