74AHC04D Description
74AHCT04 is a high-speed Si-gate CMOS device and is pin patible with Lowpower Schottky TTL (LSTTL). It is specified in pliance with JEDEC standard No. 74AHCT04 provides six inverting buffers.
74AHC04D Key Features
- Balanced propagation delays
- Inputs accept voltages higher than VCC
- Input levels
- For 74AHC04: CMOS level
- For 74AHCT04: TTL level
- ESD protection
- HBM JESD22-A114F exceeds 2000 V
- MM JESD22-A115-A exceeds 200 V
- CDM JESD22-C101C exceeds 1000 V
- Multiple package options