Datasheet Summary
74AHC257-Q100; 74AHCT257-Q100
Quad 2-input multiplexer; 3-state
Rev. 1
- 22 July 2013
Product data sheet
1. General description
The 74AHC257-Q100; 74AHCT257-Q100 is a high-speed Si-gate CMOS device and is pin patible with Low-power Schottky TTL (LSTTL). It is specified in pliance with JEDEC standard No. 7-A.
The 74AHC257-Q100; 74AHCT257-Q100 has four identical 2-input multiplexers with 3-state outputs. They select 4 bits of data from two sources and a mon data select input (S) controls them. The data inputs from source 0 (1I0 to 4I0), are selected when input S is LOW. The data inputs from source 1 (1I1 to 4I1) are selected when input S is HIGH. Data appears at the outputs (1Y to...