74AHC273-Q100 Datasheet | Nexperia

74AHC273-Q100; 74AHCT273-Q100 Octal D-type flip-flop with reset; positive-edge trigger Rev. 2 - 23 September 2020 Product data sheet 1. General description The 74AHC273-Q100; 74AHCT273-Q100 is a high-speed Si-gate CMOS device and is pin patible with Low-power Schottky TTL (LSTTL). It is specified in pliance with JEDEC standard No. 7-A. The 74AHC273-Q100; 74AHCT273-Q100 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The mon clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR input. The device is useful for applications where only the true output is required and the clock and master reset are mon to all storage elements. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features - Automotive product qualification in accordance with AEC-Q100 (Grade 1) - Specified from -40 °C to +85 °C and from -40 °C to +125 °C - Balanced propagation delays - All inputs have Schmitt-trigger actions - Inputs accept voltages higher than VCC - Ideal buffer for MOS microcontroller or memory - mon clock and master reset - Input levels: - For 74AHC273-Q100: CMOS level - For 74AHCT273-Q100: TTL level - ESD protection: - MIL-STD-883, method 3015 exceeds 2000 V - HBM JESD22-A114F exceeds 2000 V - MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω) - DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints Nexperia 74AHC273-Q100; 74AHCT273-Q100 Octal D-type flip-flop with reset; positive-edge...