74AHC374-Q100 Description
74AHCT374-Q100 is a high-speed Si-gate CMOS device and is pin patible with Low-power Schottky TTL (LSTTL). It is specified in pliance with JEDEC standard No. 74AHCT374-Q100 prises eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.
74AHC374-Q100 Key Features
- Automotive product qualification in accordance with AEC-Q100 (Grade 1)
- Specified from 40 C to +85 C and from 40 C to +125 C
- Balanced propagation delays
- All inputs have Schmitt-trigger actions
- Inputs accept voltages higher than VCC
- mon 3-state output enable input
- Input levels
- For 74AHC374-Q100: CMOS level
- For 74AHCT374-Q100: TTL level
- ESD protection
74AHC374-Q100 Applications
- Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C