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74AHCT594 - 8-bit shift register

Download the 74AHCT594 datasheet PDF. This datasheet also covers the 74AHC594 variant, as both devices belong to the same 8-bit shift register family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74AHC594; 74AHCT594 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).

It is specified in compliance with JEDEC standard No.

7-A.

Key Features

  • Wide supply voltage range from 2.0 V to 5.5 V.
  • Balanced propagation delays.
  • All inputs have Schmitt-trigger action.
  • Overvoltage tolerant inputs to 5.5 V.
  • High noise immunity.
  • CMOS low power dissipation.
  • 8-bit serial-in, parallel-out shift register with storage.
  • Independent direct overriding clears on shift and storage registers.
  • Independent clocks for shift and storage registers.
  • Latch-up performance excee.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AHC594-nexperia.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74AHC594; 74AHCT594 8-bit shift register with output register Rev. 4 — 7 July 2021 Product data sheet 1. General description The 74AHC594; 74AHCT594 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC594; 74AHCT594 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct overriding clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is provided for cascading purposes. Both the shift and storage register clocks are positive-edge triggered.