74ALVC162836ADGG Datasheet | Nexperia

74ALVC162836A 20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state Rev. 3 - 6 April 2018 Product data sheet 1 General description The 74ALVC162836A is a 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the An to Yn data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the Adata is stored in the latch/flip-flop. The 74ALVC162836A is designed with 30 Ω series resistors in both HIGH or LOW output stages. When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high...