74ALVC164245 Datasheet | Nexperia

description The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS patible TTL families. The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring non-inverting 3-state bus patible outputs in both send and receive directions. It is designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment. This device can be used as two 8-bit transceivers or one 16-bit transceiver. The direction control inputs (1DIR and 2DIR) determine the direction of the data flow. n DIR (active HIGH) enables data from n An ports to n Bn ports. n DIR (active LOW) enables data from n Bn ports to n An ports. The output enable inputs (1OE and 2OE), when HIGH, disable both n An and n Bn ports by placing them in a high-impedance OFF-state. Pins n An, n OE and n DIR are referenced to VCC(A) and pins n Bn are referenced to VCC(B). In suspend mode, when one of the supply voltages is zero, there will be no current flow from the non-zero supply towards the zero supply. The n An-outputs must be set 3-state and the voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCC(B) ≥ VCC(A) (except in suspend mode). 2. Features and benefits - Wide supply voltage range: - 3 V port (VCC(A)): 1.5 V to 3.6 V - 5 V port (VCC(B)): 1.5 V to 5.5 V - CMOS low power consumption - Overvoltage tolerant inputs to 5.5 V - Direct interface with TTL levels - IOFF circuitry provides partial Power-down mode operation - Latch-up performance exceeds 100 m A per JESD 78 Class II Level B - Control inputs voltage range from 2.7 V to 5.5 V - High-impedance outputs when VCC(A) or VCC(B) = 0 V - plies with JEDEC standards: - JESD8-7 (1.65 V to 1.95 V) - JESD8-5 (2.3 V to 2.7 V) - JESD8C (2.7 V to 3.6 V) - ESD protection: - HBM JESD22-A114F exceeds 2000 V - MM JESD22-A115-A exceeds 200 V - Specified from -40 °C to +85 °C and -40 °C to +125 °C Nexperia 16-bit dual supply translating transceiver; 3-state 3....