Datasheet4U Logo Datasheet4U.com

74ALVC16836ADGG - 20-bit registered driver

This page provides the datasheet information for the 74ALVC16836ADGG, a member of the 74ALVC16836A 20-bit registered driver family.

Datasheet Summary

Description

The 74ALVC16836A is a 20-bit universal bus driver.

Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP).

When LE is LOW, the A to Y data flow is transparent.

Features

  • Wide supply voltage range from 1.2 V to 3.6 V.
  • CMOS low-power consumption.
  • Direct interface with TTL levels.
  • Current drive ± 24 mA at 3.0 V.

📥 Download Datasheet

Datasheet preview – 74ALVC16836ADGG

Datasheet Details

Part number 74ALVC16836ADGG
Manufacturer nexperia
File Size 213.52 KB
Description 20-bit registered driver
Datasheet download datasheet 74ALVC16836ADGG Datasheet
Additional preview pages of the 74ALVC16836ADGG datasheet.

📁 Similar Datasheet

  • 74ALVC16836A - 20-bit registered driver (NXP)
  • 74ALVC16834A - 18-bit registered driver (NXP)
  • 74ALVC16835 - Low Voltage 18-Bit Universal Bus Driver (Fairchild Semiconductor)
  • 74ALVC16835A - 18-bit registered driver 3-State (NXP)
  • 74ALVC16839 - Low Voltage 20-Bit Selectable Register/Buffer (Fairchild Semiconductor)
  • 74ALVC16821 - Low Voltage 20-Bit D-Type Flip-Flops (Fairchild Semiconductor)
  • 74ALVC16827 - Low Voltage 20-Bit Buffer/Line Driver (Fairchild Semiconductor)
  • 74ALVC16841 - Low Voltage 20-Bit Transparent Latch (Fairchild Semiconductor)
  • 74ALVC162240 - Low Voltage 16-Bit Inverting Buffer/Line Driver (Fairchild Semiconductor)
  • 74ALVC162244 - Low Voltage 16-Bit Buffer/Line Driver (Fairchild Semiconductor)
Other Datasheets by nexperia

Full PDF Text Transcription

Click to expand full text
74ALVC16836A 20-bit registered driver with inverted register enable; 3-state Rev. 2 — 12 September 2018 Product data sheet 1. General description The 74ALVC16836A is a 20-bit universal bus driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flipflop. When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latch/flip-flop.
Published: |