Datasheet4U Logo Datasheet4U.com

74ALVC374 - Octal D-type flip-flop

Description

The 74ALVC374 is an octal positive-edge triggered D-type flip-flop with 3-state outputs.

Features

  • Wide supply voltage range from 1.65 V to 3.6 V.
  • 3.6 V tolerant inputs/outputs.
  • CMOS low power consumption.
  • Direct interface with TTL levels (2.7 V to 3.6 V).
  • Power-down mode.
  • Latch-up performance exceeds 250 mA.
  • Complies with JEDEC standards:.
  • JESD8-7 (1.65 V to 1.95 V).
  • JESD8-5 (2.3 V to 2.7 V).
  • JESD8B (2.7 V to 3.6 V).
  • ESD protection:.
  • HBM JESD22-A114E exceeds 2000 V.
  • MM JESD22.

📥 Download Datasheet

Datasheet preview – 74ALVC374

Datasheet Details

Part number 74ALVC374
Manufacturer nexperia
File Size 254.83 KB
Description Octal D-type flip-flop
Datasheet download datasheet 74ALVC374 Datasheet
Additional preview pages of the 74ALVC374 datasheet.

📁 Similar Datasheet

  • 74ALVC374 - Octal D-type flip-flop positive edge-trigger (NXP)
  • 74ALVC373 - Octal D-type transparent latch (NXP)
  • 74ALVC32 - Low Voltage Quad 2-Input OR Gate (Fairchild Semiconductor)
  • 74ALVC32 - Quad 2-input OR gate (NXP)
  • 74ALVC38 - Low Voltage Quad 2-Input NAND Gate (Fairchild Semiconductor)
  • 74ALVC00 - Low Voltage Quad 2-Input NAND Gate (Fairchild Semiconductor)
  • 74ALVC00 - Low Voltage Quad 2-Input NAND Gate (ON Semiconductor)
  • 74ALVC02 - Quad 2-input NOR gate (NXP)
  • 74ALVC04 - Hex inverter (Philips)
  • 74ALVC08 - Low Voltage Quad 2-Input AND Gate (Fairchild Semiconductor)
Other Datasheets by nexperia

Full PDF Text Transcription

Click to expand full text
74ALVC374 Octal D-type flip-flop; positive-edge trigger; 3-state Rev. 3 — 30 April 2021 Product data sheet 1. General description The 74ALVC374 is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops . This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Published: |