74ALVCH16652DGG Datasheet | Nexperia

74ALVCH16652 16-bit transceiver/register with dual enable; 3-state Rev. 3 - 12 September 2018 Product data sheet 1. General description The 74ALVCH16652 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, Dtype flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the ‘A’ or ‘B’, or both buses, will be stored in the internal registers, at the appropriate clock inputs (nCPAB or nCPBA) regardless of the select inputs (nSAB and nSBA) or output enable (nOEAB and nOEBA) control inputs. Depending on the select inputs nSAB and nSBA data can directly go from input to...