74ALVCH16652DGG Overview
The 74ALVCH16652 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, Dtype flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the ‘A’ or ‘B’, or both buses, will be stored in the internal registers, at the appropriate clock inputs (nCPAB or nCPBA) regardless of the select inputs (nSAB and...
74ALVCH16652DGG Key Features
- Wide supply voltage range of 1.2 V to 3.6 V
- CMOS low power consumption
- Direct interface with TTL levels
- Current drive ±24 mA at VCC = 3.0 V
- MULTIBYTE flow-through standard pin-out architecture
- Low inductance multiple VCC and GND pins for minimum noise and ground bounce
- All data inputs have bushold
- Output drive capability 50 Ω transmission lines at 85 °C
- plies with JEDEC standards
- JESD8-5 (2.3 V to 2.7 V)
