74AUP1G175 Overview
The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flop and output to be reset to LOW.
74AUP1G175 Key Features
- Wide supply voltage range from 0.8 V to 3.6 V
- High noise immunity
- CMOS low power dissipation
- plies with JEDEC standards
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
- ESD protection
74AUP1G175 Applications
- Wide supply voltage range from 0.8 V to 3.6 V
