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74AUP1G57 - Low-power configurable multiple function gate

General Description

The 74AUP1G57 is a configurable multiple function gate with Schmitt-trigger inputs.

The device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input.

All inputs can be connected directly to VCC or GND.

Key Features

  • Wide supply voltage range from 0.8 V to 3.6 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Overvoltage tolerant inputs to 3.6 V.
  • Low noise overshoot and undershoot < 10 % of VCC.
  • IOFF circuitry provides partial power-down mode operation.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II.
  • Low static power consumption; ICC = 0.9 μA (maximum).
  • Complies with JEDEC standards:.
  • JESD8-12 (0.8 V to 1.3.

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Datasheet Details

Part number 74AUP1G57
Manufacturer Nexperia
File Size 289.66 KB
Description Low-power configurable multiple function gate
Datasheet download datasheet 74AUP1G57 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74AUP1G57 Low-power configurable multiple function gate Rev. 10 — 21 January 2022 Product data sheet 1. General description The 74AUP1G57 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • Wide supply voltage range from 0.