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74AUP1T97 Datasheet

Manufacturer: Nexperia
74AUP1T97 datasheet preview

Datasheet Details

Part number 74AUP1T97
Datasheet 74AUP1T97-nexperia.pdf
File Size 276.04 KB
Manufacturer Nexperia
Description Low-power configurable gate
74AUP1T97 page 2 74AUP1T97 page 3

74AUP1T97 Overview

The 74AUP1T97 is a configurable multiple function gate with level translating, Schmitt-trigger inputs. The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; All inputs can be connected directly to VCC or GND.

74AUP1T97 Key Features

  • Wide supply voltage range from 2.3 V to 3.6 V
  • CMOS low power dissipation
  • High noise immunity
  • Overvoltage tolerant inputs to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Low static power consumption; ICC = 1.5 μA (maximum)
  • plies with JEDEC standards
  • JESD8-12 (0.8 V to 1.3 V)

74AUP1T97 Applications

  • Wide supply voltage range from 2.3 V to 3.6 V

74AUP1T97 from other manufacturers

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Brand Logo Part Number Description Other Manufacturers
Fairchild Semiconductor Logo 74AUP1T97 Low Power Configurable Gate Fairchild Semiconductor
Nexperia logo - Manufacturer

More Datasheets from Nexperia

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Part Number Description
74AUP1T98 Low-power configurable gate
74AUP1T98-Q100 Low-power configurable gate
74AUP1T00 Low-power 2-input NAND gate
74AUP1T02 Low-power 2-input NOR gate
74AUP1T04 Low-power inverter
74AUP1T08 Low-power 2-input AND gate
74AUP1T14 Low-power inverter
74AUP1T17 Low-power buffer
74AUP1T32 Low-power 2-input OR-gate
74AUP1T34 Low-power dual supply translating buffer

74AUP1T97 Distributor

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