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74AUP1T97 - Low-power configurable gate

Description

The 74AUP1T97 is a configurable multiple function gate with level translating, Schmitt-trigger inputs.

The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input.

All inputs can be connected directly to VCC or GND.

Features

  • Wide supply voltage range from 2.3 V to 3.6 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Overvoltage tolerant inputs to 3.6 V.
  • Low noise overshoot and undershoot < 10 % of VCC.
  • IOFF circuitry provides partial power-down mode operation.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II.
  • Low static power consumption; ICC = 1.5 μA (maximum).
  • Complies with JEDEC standards:.
  • JESD8-12 (0.8 V to 1.3.

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Datasheet Details

Part number 74AUP1T97
Manufacturer nexperia
File Size 276.04 KB
Description Low-power configurable gate
Datasheet download datasheet 74AUP1T97 Datasheet
Additional preview pages of the 74AUP1T97 datasheet.

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Full PDF Text Transcription

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74AUP1T97 Low-power configurable gate with voltage-level translator Rev. 8 — 27 January 2022 Product data sheet 1. General description The 74AUP1T97 is a configurable multiple function gate with level translating, Schmitt-trigger inputs. The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. Low threshold Schmitt trigger inputs allow these devices to be driven by 1.8 V logic levels in 3.3 V applications. This device ensures very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. This device is fully specified for partial power down applications using IOFF.
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