Datasheet Details
| Part number | 74AUP2G132 |
|---|---|
| Manufacturer | Nexperia |
| File Size | 305.06 KB |
| Description | Low-power dual 2-input NAND Schmitt trigger |
| Datasheet |
 74AUP2G132 Datasheet
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General Description
The 74AUP2G132 is a dual 2-input NAND gate with Schmitt-trigger inputs.
This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power down applications using IOFF.
Key Features
- Wide supply voltage range from 0.8 V to 3.6 V.
- CMOS low power dissipation.
- High noise immunity.
- Low static power consumption; ICC = 0.9 μA (maximum).
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
- Overvoltage tolerant inputs to 3.6 V.
- Low noise overshoot and undershoot < 10 % of VCC.
- IOFF circuitry provides partial Power-down mode operation.
- Complies with JEDEC standards:.
- JESD8-12 (0.8.