74AVCH16245 Datasheet | Nexperia

description The 74AVCH16245 is a 16-bit transceiver featuring non-inverting 3-state bus patible outputs in both send and receive directions. The device features two output enable inputs (n OE) for easy cascading and two send/receive inputs (n DIR) for direction control. Inputs n OE control the outputs so that the buses are effectively isolated. This device can be used as two 8-bit transceivers or one 16-bit transceiver. The 74AVCH16245 is designed to have an extremely fast propagation delay and a minimum amount of power consumption. To ensure the high-impedance output state during power-up or power-down, tie pins n OE to VCC through a pull-up resistor (Live Insertion). A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient (see Figure 4 and Figure 5) The 74AVCH16245 has active bus-hold circuitry to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2. Features and benefits - Wide supply voltage range from 1.2 V to 3.6 V - plies with JEDEC standards: - JESD8-7 (1.2 V to 1.95 V) - JESD8-5 (1.8 V to 2.7 V) - JESD8-1A (2.7 V to 3.6 V) - CMOS low power consumption - Input/output tolerant up to 3.6 V - Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation - Low inductance multiple VCC and GND pins to minimize noise and ground bounce - Supports Live Insertion - All inputs have bus-hold Nexperia 16-bit transceiver with direction pin; 3.6 V tolerant; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74AVCH16245DGG - 40 C to +85 C TSSOP48 Description plastic thin shrink small outline package; 48 leads; body width 6.1 mm 4. Functional diagram Version SOT362-1 1DIR 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 Fig 1. Logic symbol 2DIR 1OE 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 2A0 2A1 2A2 2A3 2A4 2A5...