74HC107 - Dual JK flip-flop

Product Overview

nexperia

Datasheet Details

Part number	74HC107
Manufacturer	nexperia
File Size	262.00 KB
Description	Dual JK flip-flop
Datasheet	74HC107 Datasheet
Additional preview pages of the 74HC107 datasheet.

Product details

Description

The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs.

Features

Wide supply voltage range from 2.0 V to 6.0 V.
CMOS low power dissipation.
High noise immunity.
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
Complies with JEDEC standards:.
JESD8C (2.7 V to 3.6 V).
JESD7A (2.0 V to 6.0 V).
Input levels:.
The 74HC107: CMOS levels.
The 74HCT107: TTL levels.
ESD protection:.
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V.
CD.

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Published: Jul 23, 2019 |