74HC165D Datasheet PDF - nexperia 8-bit parallel-in/serial out shift register Specs

74HC165D - 8-bit parallel-in/serial out shift register

This page provides the datasheet information for the 74HC165D, a member of the 74HC165 8-bit parallel-in/serial out shift register family.

Datasheet Summary

Description

The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers.

Features

Wide supply voltage range from 2.0 V to 6.0 V.
CMOS low power dissipation.
High noise immunity.
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
Asynchronous 8-bit parallel load.
Synchronous serial input.
Input levels:.
For 74HC165: CMOS level.
For 74HCT165: TTL level.
Complies with JEDEC standards:.
JESD8C (2.7 V to 3.6 V).
JESD7A (2.0 V to 6.0 V).
ESD protectio.

Datasheet Details

Part number	74HC165D
Manufacturer	nexperia
File Size	317.10 KB
Description	8-bit parallel-in/serial out shift register
Datasheet	74HC165D Datasheet
Additional preview pages of the 74HC165D datasheet.

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Full PDF Text Transcription

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74HC165; 74HCT165 8-bit parallel-in/serial out shift register Rev. 8 — 9 May 2025 Product data sheet 1. General description The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the CP input. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications. 2.

Published: Dec 26, 2020 |