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74HC191D - Presettable synchronous 4-bit binary up/down counter

Download the 74HC191D datasheet PDF. This datasheet also covers the 74HC191 variant, as both devices belong to the same presettable synchronous 4-bit binary up/down counter family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC191 is an asynchronously presettable 4-bit binary up/down counter.

It contains four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation.

Key Features

  • Wide supply voltage range from 2.0 to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • CMOS input levels.
  • Synchronous reversible counting.
  • Asynchronous parallel load.
  • Count enable control for synchronous expansion.
  • Single up/down control input Nexperia 74HC191 Presettable synchronous 4-bit binary up/down counter.
  • Complies with JEDEC.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC191-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HC191D
Manufacturer Nexperia
File Size 293.43 KB
Description Presettable synchronous 4-bit binary up/down counter
Datasheet download datasheet 74HC191D Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC191 Presettable synchronous 4-bit binary up/down counter Rev. 7 — 14 March 2024 Product data sheet 1. General description The 74HC191 is an asynchronously presettable 4-bit binary up/down counter. It contains four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation. Asynchronous parallel load capability permits the counter to be preset to any desired value. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs when the parallel load (PL) input is LOW. This operation overrides the counting function. Counting is inhibited by a HIGH level on the count enable (CE) input.