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74HC299D - 8-bit universal shift register

Download the 74HC299D datasheet PDF. This datasheet also covers the 74HC299 variant, as both devices belong to the same 8-bit universal shift register family and are provided as variant models within a single manufacturer datasheet.

General Description

The 74HC299 is an 8-bit universal shift register with 3-state outputs.

It contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and hold operations.

Key Features

  • CMOS input levels.
  • Multiplexed inputs/outputs provide improved bit density.
  • Four operating modes:.
  • Shift left.
  • Shift right.
  • Hold (store).
  • Load data.
  • Operates with output enable or at high-impedance OFF-state.
  • 3-state outputs drive bus lines directly.
  • Cascadable for n-bit word lengths.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • Speci.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC299-nexperia.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 74HC299D
Manufacturer Nexperia
File Size 264.40 KB
Description 8-bit universal shift register
Datasheet download datasheet 74HC299D Datasheet

📁 Similar Datasheet

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74HC20 Dual 4-input NAND gate Philips

Other Datasheets by Nexperia

Part Number Description
74HC299 8-bit universal shift register
74HC20 Dual 4-input NAND gate
74HC20-Q100 Dual 4-input NAND gate
74HC20D Dual 4-input NAND gate
74HC21 Dual 4-input AND gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC299 8-bit universal shift register; 3-state Rev. 6 — 11 May 2021 Product data sheet 1. General description The 74HC299 is an 8-bit universal shift register with 3-state outputs. It contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and hold operations. The type of operation is determined by the mode select inputs S0 and S1. Pins I/O0 to I/O7 are flip-flop 3-state buffer outputs which allow them to operate as data inputs in parallel load mode. The serial outputs Q0 and Q7 are used for expansion in serial shifting of longer words. A LOW signal on the asynchronous master reset input MR overrides the Sn and clock CP inputs and resets the flip-flops.